Memory Chip Design
Q1.
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11-IA0 are connected to the address port of these blocks. The chip select (CS) is active high. The input memory addresses (IA11-IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?Q2.
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A_{15} \; to \; A_0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?Q5.
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M x 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.Q6.
Suppose you want to build a memory with 4 byte words and a capacity of 2^{21} bits. What is type of decoder required if the memory is built using 2K \times 8 RAM chips?Q7.
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 \times 6 array, where each chip is 8K \times 4 bits ?Q9.
A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes 100 nsec. What percentage of the memory cycle time is used for refreshing?Q10.
The process of organizing the memory into two banks to allow 8-and 16-bit data operation is called